MIPS Assembly/MIPS Architecture

The MIPS architecture

MIPS is a register based architecture, meaning the CPU uses registers to perform operations on. There are other types of processors out there as well, such as stack-based processors and accumulator-based processors.

Registers are memory just like RAM, except registers are much smaller than RAM, and are much faster. In MIPS the CPU can only do operations on registers, and special immediate values.

MIPS processors have 32 general purpose registers, but some of these are reserved. A fair number of registers however are available for your use. For example, one of these registers, the program counter, contains the memory address of the next instruction to be executed. As the processor executes the instruction, the program counter is incremented, and the next memory address is fetched, executed, and so on.

Why MIPS?

The MIPS architecture is a Reduced Instruction Set Computer (RISC). As a RISC architecture, it doesn't assign individual instructions to complex, logically intensive tasks. This is in contrast to complex instruction set computer (CISC) architectures like the DEC VAX, which had an instruction to multiply polynomials and another to perform a cyclic redundancy check (CRC), often used in TCP/IP. At the time, it was thought that implementing such instructions in hardware would result in performance increase for programs that used them, even if it resulted in highly complex processor design. MIPS and other RISC architectures were based on the philosophy that, among other things, by only implementing a small core (only a few dozen instructions, instead of several hundred) of the most common instructions, architects could simplify the design and speed up the majority of common instructions so much that the cost of implementing complex programs as multiple instructions would be hidden.

Much has been written on the RISC versus CISC debate,^[1][2][3][4] so for our purposes we shall focus on the consequences of the MIPS design choices:

• All MIPS instructions are 32 bits long.
  • This makes hardware for accessing and decoding instructions straightforward.
  • This also means there are a finite number of instructions.
• All MIPS instructions belong to one of three instruction formats. This makes decoding instructions simple for both humans and hardware. Since the instruction format is regular, it doesn't take much work to learn most of the MIPS instruction set.

MIPS Philosophies

• Simplicity favors regularity
• Good design demands good compromise
• Smaller is faster
• Make the common tasks the fastest

1. ↑ John Mashey on RISC/CISC
2. ↑ RISC vs. CISC
3. ↑ Patterson, D. A. & Ditzel, D. R. (1980). The Case for the Reduced Instruction Set Computer. SIGARCH Computer Architecture News, 8(6), 25-33.
4. ↑ Clark, D. W. & Strecker W. D. (1980). Comments on 'The case for the reduced instruction set computer' by Patterson and Ditzel. SIGARCH Computer Architecture News, 8(6), 34-38.